The invention relates to a pulse generator for integrated circuits.
In order to drive integrated circuits, for example dynamic random access memories (DRAMs), with pulses, input pulses are needed which have a defined minimum pulse length. Here, the problem often occurs that the pulse length of an output pulse derived from a very short input signal by using conventional pulse generator circuits cannot be produced with the desired reliability and stability.
Using a conventional pulse generator circuit, an output pulse with a guaranteed maximum pulse length can be generated from an input signal represented by a leading edge. The pulse generator circuit contains a NAND element which has two inputs, one input being supplied with the input signal undelayed and the other input being supplied with an input signal delayed by a delay element. The output from the NAND element goes low when the state of both input signals through the NAND element is high, that is to say only when the change in potential from low to high, representing the input signal, has also reached the second input of the NAND element after being delayed by the delay element. Following inversion by an inverter element, a pulse-like output signal is output at the output terminal, the length of the pulse being determined by the delay time of the delay element. However, the generation of the output pulse is impossible or undefined when an input signal decays again in a shorter time than the delay time of the delay element, since at the time at which the second input to the NAND element goes high, the potential at the first input to the NAND element has already gone low again.
German Patent DE 21 37 068 B2 includes a description of a circuit configuration for suppressing interfering pulses, in which one input leads via a direct connection to a reset input of a bistable flip-flop circuit or to a time-determining stage. The bistable flip-flop stage is constructed from first NAND elements. The time-determining stage contains a high-pass filter with a downstream inverting, potential-controlled flip-flop circuit, which is formed by a second NAND element. This circuit configuration is overall preceded by a further NAND element, in order to process inverted input pulses. The first NAND elements are cross-coupled, and an output signal contains only that part of a useful pulse from an input signal that exceeds a maximum suppression time. Moreover, Published, Japanese Patent Application JP 0059161912 A discloses a pulse generator circuit in which an input signal is fed to a delay element and an output signal is selected by a selection circuit in an operating mode. The inverted signal from the input signal is then supplied to an AND element, which outputs a clock pulse. A further signal, which is sent through an additional delay element in a test mode, is selected by the selection circuit. A broad clock pulse is therefore obtained, and the signal transmission time between locking elements is checked.
Finally, Published, Non-Prosecuted German Patent Application DE 28 07 409 A1 discloses a circuit configuration for coupling out pulses in which the NOR elements are used for buffering.
It is accordingly an object of the invention to provide a pulse generator that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which, in particular, is suitable for application in integrated circuits and which can generate an output pulse with a defined minimum pulse length even in the case of input signals which last for a very short time.
With the foregoing and other objects in view there is provided, in accordance with the invention, a pulse generator.
The pulse generator contains a NOR gate having a first input, a second input, and an output. An inverter is provided and has an input connected to the output of the NOR gate and an output. An output terminal is connected to the output of the inverter. An input terminal for receiving an input signal is connected directly, via a first signal path, to the first input of the NOR gate. A delay element having an input connected to the input terminal and an output is provided. The delay circuit receives the input signal and delays propagation of the input signal by a delay time. A buffer circuit having a first input connected, via a second signal path, to the input terminal, a second input connected to the output of the delay element, and an output connected to the second input of the NOR gate, is provided. The buffer circuit receives and is set by the input signal virtually without delay. The buffer circuit is reset after an expiry of the delay time defined by the delay element and leads to a generation of an output pulse with a defined minimum pulse length available at the output terminal if the input signal is less than the delay time, and if the input signal is longer than the delay time, a pulse length of the output pulse is defined by a pulse length of the input signal.
The buffer circuit, which can be particularly simply implemented by two cross-coupled NAND elements, guarantees that an input signal A, represented here by way of example by a change in a signal from low to high and which is initially transmitted directly to the output terminal, that is to say essentially without delay, is at the same time buffered in the buffer circuit.
The high state buffered in the buffer circuit defines the pulse of the output signal, that is to say its minimum pulse length. Buffering in the buffer circuit is cancelled when the change in the input signal from low to high has been propagated through the inverter chain. The input signal is then again exclusively responsible for the definition of the output pulse.
For the functioning of the proposed pulse generator circuit, the only precondition is that the length of the input signal is longer than the time which is needed for the buffering operation, on the basis of gate delay times. As a result of the buffering, a minimum pulse length of the output pulse is guaranteed, and is independent of the length of the input signal.
The pulse generator according to the invention has inverting elements connected in series, a logic combining element and a delay element. The buffer circuit connected downstream of the delay element and the input terminal ensures that even in the case of an input signal with a very short duration an output pulse generated from the input signal is guaranteed to have a minimum pulse length.
The significant feature in the pulse generator is, then, the specific configuration of the combining element from a NOR element and leading the input signal via two different signal paths.
The invention therefore permits a pulse generator in which the maximum pulse length of an output pulse is defined in a simple way by the duration of the input signal, and the minimum pulse length of the output pulse is defined by the delay time of a delay element.
In accordance with an added feature of the invention, the buffer circuit has two cross-coupled NAND elements.
In accordance with another feature of the invention, the buffer circuit has two cross-coupled NOR elements.
In accordance with an additional feature of the invention, the input signal is represented by a change in potential from low to high, and the output signal is a positive pulse.
In accordance with a further feature of the invention, the buffer circuit has a third input, which serves as an enable input, to which an enable signal can be supplied.
In accordance with an another added feature of the invention, a further inverter having a first terminal connected to the input terminal and a second terminal connected to the delay element and to the buffer circuit, is provided.
In accordance with a concomitant feature of the invention, an additional inverter having a first terminal connected to the output terminal of the buffer circuit and a second terminal connected to the second input of the NOR gate, is provided.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a pulse generator, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.